Demystifying PL-PS Interrupts and Device Tree Configuration on the Zynq UltraScale+
Reading Time: 3 minutes Introduction and Problem The AMD Zynq Ultrascale+ contains many available interrupt sources in its design. Most notably, are the interrupt channels available between the PL (Programmable Logic / FPGA) and the PS (processing system). This enables FPGA IP within the device to trigger interrupts in software. Although this high-level concept is relatively simple, the intricate […]
Demystifying PL-PS Interrupts and Device Tree Configuration on the Zynq UltraScale+ Read More »
