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Enabling Watchdog Timers on the Zynq Ultrascale+ MPSoC: Step by Step

Leave a Comment / Embedded Linux, FPGAs, Watchdog Timer

Reading Time: 5 minutes Introduction Today’s Embedded systems have become quite complex, often containing multiple processors and software. As such, the risk of a system locking up becomes more of a concern. To that end, watchdog timer peripherals have become an integral part of these systems. A hardware watchdog timer is a type of timer that, once enabled, requires […]

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Leveraging Systemd for Hardware Watchdog Control in Embedded Linux

Leave a Comment / Embedded Linux

Reading Time: 3 minutes Introduction In embedded systems, the hardware watchdog timer is a crucial yet often overlooked feature, especially in Linux systems. Many modern system-on-chips (SoCs) include an internal watchdog timer with upstream Linux support. With the growing complexity and extensive software suite of a custom Embedded Linux system, it is possible for such systems to experience freezing

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Controlling Zynq Ultrascale+ pl_resetn Signals in Software

Leave a Comment / Embedded Linux, FPGAs

Reading Time: 5 minutes Introduction Oftentimes, it is desirable for a system to be able to dynamically control the FPGA logic resets in software. There are a number of reasons for this, but throughout my career, I have found that when developing and testing the software for an FPGA, you often may run into situations where due to mistakes

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