zynq

Enabling Watchdog Timers on the Zynq Ultrascale+ MPSoC: Step by Step

Reading Time: 5 minutes Introduction Today’s Embedded systems have become quite complex, often containing multiple processors and software. As such, the risk of a system locking up becomes more of a concern. To that end, watchdog timer peripherals have become an integral part of these systems. A hardware watchdog timer is a type of timer that, once enabled, requires […]

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Demystifying PL-PS Interrupts and Device Tree Configuration on the Zynq UltraScale+

Reading Time: 3 minutes Introduction and Problem The AMD Zynq Ultrascale+ contains many available interrupt sources in its design. Most notably, are the interrupt channels available between the PL (Programmable Logic / FPGA) and the PS (processing system). This enables FPGA IP within the device to trigger interrupts in software. Although this high-level concept is relatively simple, the intricate

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Controlling Zynq Ultrascale+ pl_resetn Signals in Software

Reading Time: 5 minutes Introduction Oftentimes, it is desirable for a system to be able to dynamically control the FPGA logic resets in software. There are a number of reasons for this, but throughout my career, I have found that when developing and testing the software for an FPGA, you often may run into situations where due to mistakes

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